• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    Disclosed is a method of planarizing a semiconductor manufacturing process which can reduce a throughput time of a semiconductor device by reducing a process time required for a chemical mechanical polishing process. To this end, the present invention comprises the steps of forming a predetermined pattern on the semiconductor substrate, forming a first planarization interlayer insulating film for local planarization on the predetermined pattern, and 200 to 300 ℃ on the first planarization interlayer insulating film for local planarization Forming a second planarization interlayer insulating film made of TEOS deposited at a temperature; and performing chemical mechanical polishing (CMP) on the resultant formed second interlayer insulating film. A method of planarizing the process is provided. Here, the second interlayer dielectric film is a TEOS (Tera Ethyl Otho Silicate) film formed by plasma chemical vapor deposition (PECVD), and the formation conditions are TEOS and oxygen supply ratio (TEOS / O 2 ) of 1.5 to 2 , and RF power. The range is 250 to 300, and the spacing between the susceptor and the shower header of the plasma chemical vapor deposition apparatus is suitably formed in the range of 300 to 400 mils.
    公开号:KR19990031574A
    申请号:KR1019970052355
    申请日:1997-10-13
    公开日:1999-05-06
    发明作者:김선래
    申请人:윤종용；삼성전자 주식회사；
    IPC主号:
    专利说明:

    Planarization method of semiconductor manufacturing process
    The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a planarization method used in the manufacturing process of a semiconductor device.
    As the degree of integration of semiconductor devices increases, the necessity of multi-layered wiring has gradually increased as researches for satisfying this progress from various angles. In forming the multi-layered wiring, the role of the inter-metal dielectric (IMD) to insulate the wiring of the lower layer and the wiring of the upper layer is very important, and the planarization of the interlayer insulating film is a picture of the subsequently formed upper layer. In the process, the importance is further emphasized because it affects the depth of focus of the stepper and causes the margin to narrow. This problem is also the same in the interlayer dielectric (ILD).
    As a method for planarizing the interlayer insulating film, a method of depositing boron and phosphorus doped silicate glass (Boro-Phosphor Silicate Glass (BPSG)) and then reflowing (Spin On Glass) SOG) is deposited and then etched back, and an interlayer insulating film is deposited, followed by chemical mechanical polishing (CMP).
    A method of planarizing an interlayer insulating film using conventional chemical mechanical polishing (CMP) is disclosed in US Pat. No. 5494854 (Title: Enhancement in throughput and planarity during CMP using a dielectric stack containing HDP-SiO sub.2 films, Date : 1996, 02.17).
    According to the prior art, after forming a predetermined pattern on a semiconductor substrate, a first dielectric seed layer is deposited, and then a second dielectric filling layer is formed to fill a gap between the predetermined patterns. ), And finally, chemical mechanical polishing (CMP) is performed while a third insulating layer (dielectric polish layer) for global planarity is laminated. In this case, the third insulating layer (dielectric polish layer) for the global planarity is to be deposited (deposition) to a sufficient thickness of 10000 Pa or more at 380 ~ 420 ℃ temperature conditions.
    In the above-described prior art, the film quality of the third insulating film for global planarization, which is thickly formed at 380 to 420 ° C., is hard, resulting in a long time for chemical mechanical polishing.
    The technical problem to be achieved by the present invention is to plan the semiconductor manufacturing process that can reduce the overall wafer time by adjusting the deposition conditions of the interlayer insulating film deposited for global planarization to shorten the time required for the chemical mechanical polishing process To provide.
    1 is a flowchart illustrating a planarization method of a semiconductor manufacturing process according to the present invention.
    According to an aspect of the present invention, there is provided a method of forming a predetermined pattern on a semiconductor substrate, forming a first interlayer insulating film for local planarization on the predetermined pattern, and forming a first interlayer for local planarization. Forming a second planarization interlayer insulating film made of TEOS deposited at a temperature of 200 to 300 ° C. on the insulating film, and performing chemical mechanical polishing (CMP) on the resultant formed second interlayer insulating film. It provides a planarization method of a semiconductor manufacturing process comprising a.
    According to a preferred embodiment of the present invention, it is preferable that the first interlayer insulating film for local planarization uses an oxide film formed using USG (Undoped Silicate Glass) or high density plasma (HDP) equipment, and the second interlayer insulating film is TEOS (Tera Ethyl Otho Silicate) film formed by Plasma Chemical Vapor Deposition (PECVD), forming conditions are 1.5 ~ 2 of TEOS and oxygen supply ratio (TEOS / O 2 ) and RF power of 250 ~ 300 For example, the spacing between the susceptor and the shower header of the plasma chemical vapor deposition apparatus is suitably formed in the range of 300 to 400 mils.
    The method may further include curing after the chemical mechanical polishing (CMP) process and depositing a capping oxide film formed by plasma chemical vapor deposition (PECVD). Do.
    According to the present invention, in the planarization method of the semiconductor manufacturing process, the overall wafer time is reduced by controlling the deposition conditions of the interlayer insulating film deposited for global planarization, thereby shortening the time required for the chemical mechanical polishing (CMP) process. Can be reduced.
    Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
    1 is a flowchart illustrating a planarization method of a semiconductor manufacturing process according to the present invention.
    Referring to FIG. 1, in the planarization method of a semiconductor manufacturing process according to the present invention using chemical mechanical polishing (CMP), a desired predetermined pattern is first formed on a semiconductor substrate through a photolithography process (100). . Subsequently, a first planarization interlayer insulating film for locally planarization filling a narrow space between the patterns is formed 200 on the predetermined pattern. At this time, the first interlayer insulating film is a film having excellent conformality that can eliminate the step generated in the process of forming the predetermined pattern. It is suitable to be an oxide film formed using Undoped Silicate Glass (HDP) or High Density Plasma (HDP) equipment. When the oxide film formed by using the high density plasma (HDP) equipment is used as the first interlayer insulating film, deposition and sputter etching can be performed in-situ at the same time. have.
    Subsequently, a second planarization interlayer insulating film for global planarization is formed on the semiconductor substrate on which the first interlayer insulating film is formed to be thick (300) by using a TEOS film by plasma enhanced chemical vapor deposition (PECVD). Since the main variable that determines the polishing time in the chemical mechanical polishing (CMP) process for planarization is the property of the second interlayer insulating film for global planarization, the method of forming the second interlayer insulating film is a major means for achieving the object of the present invention. do. In the present invention, the temperature at which the TEOS film is formed by PECVD is in the low temperature range of 200 to 300 ° C., which is lower than that of the prior art. TEOS and oxygen supply ratio (TEOS / O 2 ) is in the range of 1.5 to 2 , RF power is in the range of 250 to 300, and between the susceptor and the shower header of the plasma chemical vapor deposition equipment. By adjusting the spacing in the range of 300 to 400 mils, a second interlayer insulating film having a porous film quality, such as a TEOS film, is formed 300 by reducing the dissociation of the reaction gas forming the TEOS film. The chemical mechanical polishing process is continuously performed 400 on the resultant product on which the second interlayer insulating film is formed. Here, the second interlayer insulating film having the porous film quality described above has a much better CMP removal rate than the conventional planarization interlayer insulating film formed at a temperature range of 380 to 420 ° C. The CMP removal rate of the interlayer insulating film formed according to the prior art is 2500-3500 Pa / min, whereas the porous second interlayer insulating film formed in the temperature range of 200-300 ° C. according to the present invention is polished and removed. The CMP removal rate is improved to 3500-4500 mW / min, saving about 30% of polishing time. Therefore, it becomes a means to reduce the overall manufacturing time (throughput time) for manufacturing a semiconductor device.
    Subsequently, the resultant of the chemical mechanical polishing (CMP) is cured in a temperature range of 300 to 400 ° C., and finally, a capping oxide film formed by plasma chemical vapor deposition (PECVD) is deposited ( 600) to complete the planarization process of the semiconductor manufacturing process according to the present invention.
    The present invention is not limited to the above embodiments, and it is apparent that many modifications can be made by those skilled in the art within the technical spirit to which the present invention belongs.
    Therefore, according to the present invention described above, semiconductor manufacturing that can reduce the overall wafer time by adjusting the deposition conditions of the interlayer insulating film deposited for global planarization to shorten the time required for the chemical mechanical polishing (CMP) process The planarization method of a process can be realized.
    权利要求:
    Claims (8)
    [1" claim-type="Currently amended] Forming a predetermined pattern on the semiconductor substrate;
    Forming a first interlayer insulating film for local planarization on the predetermined pattern;
    Forming a global planarization second interlayer insulating film made of TEOS deposited at a temperature of 200 to 300 ° C. on the first planarization interlayer insulating film; And
    And performing chemical mechanical polishing (CMP) on the resultant material on which the second interlayer insulating film is formed.
    [2" claim-type="Currently amended] The method of claim 1, wherein the first interlayer insulating film for local planarization comprises an oxide film formed using USG (Undoped Silicate Glass) or high density plasma (HDP) equipment.
    [3" claim-type="Currently amended] The method of claim 1, wherein the second interlayer dielectric layer is formed by plasma chemical vapor deposition (PECVD).
    [4" claim-type="Currently amended] 4. The method of claim 3, wherein the plasma chemical vapor deposition (PECVD) has a TEOS, oxygen (O 2 ), and a feed ratio (TEOS / O 2 ) of 1.5 to 2 .
    [5" claim-type="Currently amended] 4. The method of claim 3, wherein the plasma chemical vapor deposition (PECVD) has a RF power in the range of 250 to 300 Watts.
    [6" claim-type="Currently amended] 4. The semiconductor fabrication method as claimed in claim 3, wherein the plasma chemical vapor deposition (PECVD) is performed at intervals of 300 to 400 mils between the susceptor and the shower header of the plasma vapor deposition apparatus. Method of planarization of the process.
    [7" claim-type="Currently amended] 2. The method of claim 1, further comprising curing after the chemical mechanical polishing step.
    [8" claim-type="Currently amended] 8. The planarization method of claim 7, further comprising depositing a capping oxide film formed by a plasma chemical vapor deposition (PECVD) method after the curing process. Way.
    类似技术:
    公开号 | 公开日 | 专利标题
    US9396986B2|2016-07-19|Mechanism of forming a trench structure
    KR101027216B1|2011-04-06|Method for forming an air gap in multilevel interconnect structure
    US8133797B2|2012-03-13|Protective layer to enable damage free gap fill
    US6835995B2|2004-12-28|Low dielectric constant material for integrated circuit fabrication
    US5426076A|1995-06-20|Dielectric deposition and cleaning process for improved gap filling and device planarization
    KR100413908B1|2004-01-07|Protective hardmask for producing interconnect structures
    US6348407B1|2002-02-19|Method to improve adhesion of organic dielectrics in dual damascene interconnects
    KR100430046B1|2004-05-03|Process for etching oxide using hexafluorobutadiene or related hydroflourocarbons and manifesting a wide process window
    DE69535438T2|2007-12-13|Method for planarizing dielectrics in semiconductor devices
    US7183201B2|2007-02-27|Selective etching of organosilicate films over silicon oxide stop etch layers
    US7052997B2|2006-05-30|Method to form etch and/or CMP stop layers
    US7888273B1|2011-02-15|Density gradient-free gap fill
    US5872064A|1999-02-16|DSAD process for deposition of inter layer dielectric
    US7326651B2|2008-02-05|Method for forming damascene structure utilizing planarizing material coupled with compressive diffusion barrier material
    KR100624566B1|2006-09-19|semiconductor device with flowable dielectric on capacitor and method for fabricating the same
    US6291334B1|2001-09-18|Etch stop layer for dual damascene process
    KR100308447B1|2001-11-30|How to deposit a layer on a substrate
    KR100498454B1|2005-07-01|Method for creating a damascene interconnect using a two-step plating process
    KR101426483B1|2014-08-11|Method for fabricating semiconductor device
    US7297640B2|2007-11-20|Method for reducing argon diffusion from high density plasma films
    US5953635A|1999-09-14|Interlayer dielectric with a composite dielectric stack
    TWI414040B|2013-11-01|Boron nitride and boron-nitride derived materials deposition method
    US7384693B2|2008-06-10|Diamond-like carbon films with low dielectric constant and high mechanical strength
    US6903004B1|2005-06-07|Method of making a semiconductor device having a low K dielectric
    US6624091B2|2003-09-23|Methods of forming gap fill and layers formed thereby
    同族专利:
    公开号 | 公开日
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    法律状态:
    1997-10-13|Application filed by 윤종용, 삼성전자 주식회사
    1997-10-13|Priority to KR1019970052355A
    1999-05-06|Publication of KR19990031574A
    优先权:
    申请号 | 申请日 | 专利标题
    KR1019970052355A|KR19990031574A|1997-10-13|1997-10-13|Planarization method of semiconductor manufacturing process|
    [返回顶部]